A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is a flash EEPROM device (also referred to as “flash memory”).
Each nonvolatile memory device has its own unique characteristics. For example, the memory cells of an EPROM device are erased using an ultraviolet light, while the memory cells of an EEPROM device are erased using an electrical signal. In a conventional flash memory device blocks of memory cells are simultaneously erased (what has been described in the art as a “flash-erasure”). The memory cells in a ROM device, on the other hand, cannot be erased at all. EPROMs, and EEPROMs, including flash memory, are commonly used in computer systems that require reprogrammable nonvolatile memory.
Two common types of flash memory architectures are the “NAND” and “NOR” architectures, so called for the resemblance which the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuit, respectively. In the NOR architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word lines and their drains are connected to bit lines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. The data values of memory cells in a selected row are placed on the bit lines based on the application of a current from the connected source line to the connected bit lines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell are connected by rows to word lines. However, each memory cell is not directly connected to a source line and a bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more, where the memory cells in the string are connected together in series, source to drain, between a common source line and a bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. In addition, the word lines connected to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by. a higher gate voltage so as to operate them as pass transistors, allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the bitline to the source line through the channel of each memory cell of the connected string, restricted only by the memory cells of each string that are selected to be read. Thereby, the current encoded stored data values of the row of selected memory cells are placed on the bit lines.
Generally, in a single level flash memory device, a charged floating gate represents one logic state, e.g., a logic “0”, while a non-charged floating gate represents the opposite logic state e.g., a logic “1”. A memory cell of a flash array is programmed by placing the floating gate into one of these charged states. Charges may be injected or written onto the floating gate by any number of methods, including e.g., avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron (CHE) injection. The floating gate may be discharged or erased by any number of methods including e.g., Fowler-Nordheim tunneling. Multi-level programmable flash memory cells are also known.
FIG. 1 illustrates a conventional memory device 10 (e.g., a NAND flash memory device). The memory device 10 includes a memory array 20, sense amplifiers 30, an output data cache 40 and a controller 50. The controller 50 controls operation of the device 10 and, as part of its operation, monitors an address pointer 60, which may be part of an address register, input/output controller, or other logic device on the device 10, that is used to readout, byte-by-byte, data from the cache 40. Typically, NAND flash memory devices contain banks of memory, each bank including its own array 20, sense amplifiers 30 and data cache 40.
FIG. 1 illustrates the device 10 performing a data readout of cached page x data (from cache 40) while simultaneously performing a fetch of page x+1 data from the array 20 into the sense amplifiers 30. The readout from the cache 40 is a sequential, byte-by-byte, readout under the control of the pointer 60, beginning from byte 0 and ending at the last byte in the page (shown as byte 2111). During these operations, the controller 50 sets the status of the read/busy indicator to “busy,” which may be monitored by an application or other system component. Since each byte of data takes about 25 ns to be readout of the cache 40, a whole page of 2112 bytes will take about 50 μs. A data fetch operation takes about 20-25 μs. Thus, as shown in FIG. 1, the system/application utilizing the device 10 can typically hide the data fetch time during the sequential data output time of 50 μs.
Referring now to FIG. 2, once the sequential output of the cached page (i.e., page x) is finished, the controller 50 can issue a transfer command to send page x+1 data from the sense amplifier 30 to the cache 40. Referring to FIG. 3, once the transfer is complete, the controller 50 will initiate a data fetch operation for the next page (i.e., page x+2) and the address pointer 60 will begin the sequential, byte-by-byte, readout of the cached page x+1 data (beginning from byte 0). The transfer illustrated in FIG. 2 takes finite amount of time, usually around 2 μs. The issuance of the transfer command and the approximate time to perform the transfer effectively interrupts the data output operation (FIG. 3), which slows down the output throughput of the device 10. The system/application utilizing the device 10 may also suffer additional overhead in hardware and/or software execution time. These effects are undesirable.